The invention relates to a semiconductor device, and more particularly, to a connection structure for input/output pads of the semiconductor device.
Generally in a packaged LSI, a chip and a package are interconnected by bonding wires. The chip is centrally formed and includes an internal logic circuit. The upper surface of the chip is formed with a plurality of I/O pads around its outer periphery. These pads are used to feed power to and for input/output of signals to and from the internal logic circuit. The pads are interconnected with lead electrodes which are exposed outside the package by means of bonding wires.
A first example of a conventional connection structure for an I/O pad 11 will be described with reference to FIGS. 1(a) and 1(b). FIG. 1(a) is a top plan view of the pad 11, and FIG. 1(b) is a cross-sectional view taken along line 1b--1b of FIG. 1(a).
An interlayer film 12, such as an oxide film, is disposed below the pad 11 which is substantially square in configuration. A wiring 13 is disposed below the pad 11. The pad 11 and the wiring 13 are interconnected via a plurality of contacts 14 that are aligned along each side of the pad 11. An automatic wire bonder, not shown, bonds a bonding wire 15 to a central region of the pad 11.
The pad 11 has a plurality of depressions 16 of a very small depth in its upper surface at locations which correspond to the contacts 14. The depressions 16 are formed when the pad 11 is formed. Because the depressions 16 are located around the outer edges of the pad 11, the upper surface of the pad 11 exhibits a high level of flatness which insures that there is an extensive area for bonding between the pad 11 and the wire 15, thus allowing a reliable connection between the pad 11 and the wire 15.
The pad 11 is interconnected with the wiring 13 via the contacts 14 which are disposed along the outer edges of the pad 11. This means that the number of interconnections between the pad 11 and the wiring 13 is small, leading to a low connection strength of the pad 11. In order to provide a higher level of integration, integrated circuits use multiple wiring layers and the contacts 14 are made much thinner than before. This further contributes to reducing the connection strength of the pad 11.
Reduced connection strength of the pad 11 presents a problem in the bonding process. When the bonder affixes the wire 15 to the pad 11, an upward force is applied to the pad 11 by the wire 15 which may separate the pad 11 from the interlayer film 12 or the interlayer film 12 from the wiring 13. Because no connection via the contacts 14 is made to the wiring 13 from the central region of the pad 11, the central region of the pad 11 is particularly susceptible to separation.
A second example of a conventional pad connection structure which is designed to exhibit an increased strength against the upward force caused by the wire 15 will be described with reference to FIGS. 2(a) and 2(b). A pad 11a is interconnected with a wiring 13 via contacts 14 which are located at equal intervals over the entire surface of the pad 11a. The number of interconnections between the pad 11a and the wiring 13 or the contacts 14 is increased, and hence the pad 11a is firmly secured to the wiring 13 (and also to the interlayer film 12). Separation of the pad 11a from either the interlayer film 12 or the wiring 13 is prevented, although an upward force is still applied to the pad 11 during the bonding operation.
However, because a number of depressions 16, which corresponds to the number of contacts 14, are formed in the upper surface of the pad 11, the surface flatness of the pad 11a is reduced, which reduces an area on the upper surface of the pad 11a for bonding with wire 15. Accordingly, the wire 15 is susceptible to separation from the pad 11a, resulting in a degradation in the reliability of the integrated circuit.
It is an object of the invention to provide a semiconductor device with an increased pad connection strength.